1. Field of the Invention
The present invention relates to a microprocessor having a built-in Dynamic Random Access Memory (DRAM) and a data transfer method thereof to be used in systems for processing a large number of data items such as image processing systems.
2. Description of the Prior Art
FIG. 12 is a diagram showing a configuration of a conventional microprocessor having a built-in DRAM. In FIG. 12, the reference number 1 designates a camera to photograph images, 2 denotes an image input section for inputting image data photographed through the camera 1 and then for performing as a master of a system bus 3 and for outputting an access signal to a built-in DRAM 4. The reference number 3 indicates the system bus having a plurality of lines, and 4 designates the DRAM connected to the system bus 3. The reference number 8 designates a bus interface unit capable of receiving image data transferred from the image input section 2 and capable of transferring the image data to the DRAM 4 through the system bus 3, and capable of transferring operation results stored in the DRAM 4 to an image output section 6 through the system bus 3 when receiving an interrupt signal transferred from the image input section 2. The reference number 6 denotes the image output section capable of outputting the operation results stored in the DRAM 4 and obtained by the execution of a central processing unit (CPU) 5, 7 indicates a display device for displaying image data as the operation results transferred from the image output section 6. The reference number 5 designates the CPU for performing image processing on the data items stored in the DRAM 4 that have been transferred from the image input section 2 and for transferring the operation result of the image processing to the DRAM 4.
Next, a description will be given of the operation of the conventional microprocessor having a built-in DRAM shown in FIG.12.
First, when the camera 1 photographs an image, the image input section 2 receives the image data photographed by the camera 1 and then transfers a transfer request to the bus interface unit 8. This transfer request is the request to transfer the image data to the DRAM 4.
When receiving the transfer request sent from the image input section 2, the bus interface unit 8 transfers the image data obtained by the image input section 2 to the DRAM 4 through the system bus 3.
In this conventional case, because the size of the image data is a larger size, it is required for the bus interface unit 8 to perform the data transfer operation many times in order to completely output the image data items to the DRAM 4. For example, when the system bus 3 has the function to output a 32 bit data item to the DRAM 4 at a time, the data transfer operation must be repeated several times until the image data items are transferred completely to the DRAM 4. The number of the repeat times of the data transfer operation to the DRAM 4 may be calculated by dividing the size of the image data items by thirty two (32).
The CPU 5 performs the image processing operation by using the image data stored in the DRAM 4 and then transfers the operation result to the DRAM 4. The DRAM 4 stores the operation result transferred from the CPU 5.
When receiving the data transfer request, sent from the image output section 6, to transfer the operation result stored in the DRAM 4, the bus interface unit 8 transfers the operation result from the DRAM 4 to the image output section 6 through the system bus 3.
After this operation, the image output section 6 transfers the operation result to the display device 7. The display device 7 then displays the received operation result to operators.
Because the conventional microprocessor having a built-in DRAM has the configuration described above, when an user requests to increase the entire operation speed of a system including the conventional microprocessor having a built-in DRAM under the condition in which a large size of image data is processed, it is difficult to increase the entire operation speed of the system even if the through-put of the CPU 5 may be increased because the system bus 3 is repeatedly used for both the data transfer from the image input section 2 to the DRAM 4 and the data transfer from the DRAM 4 to the image output section 6, that is, because the frequency of use of the system bus 3 is increased. This becomes a bottle-neck for the entire processing speed of the system. In addition to this drawback, because there is a drawback that the system bus 3 has the limitation of the data transfer speed, it is difficult to increase the data transfer speed of the system according to a request. As a result, it is difficult to increase the processing speed of the entire system.